A typical wireless communication receiver includes a down converter stage in order to translate a received radio frequency carrier signal to an intermediate frequency (IF) signal and thereafter (or direct) to a baseband signal. Many current wireless communication systems employ digital technology, which introduces complexity into the receiver's down converter stage, whereby an input radio frequency signal is divided and multiplied by a local oscillator signal and a quadrature version of the local oscillator signal. The resulting outputs are known as the in-phase (I) and quadrature (Q) components. Filtering and amplification in the analogue stages typically precede analogue to digital conversion and subsequent filtering and amplification in the digital domain.
A recent development in wireless communications has introduced short-range wireless capabilities to wireless communication units, e.g. Bluetooth™ and WiFi™. For example, the Internet of Things (IoT) market is a booming technology area investigating Wi-Fi™ technology for many low power consumption products.
Most radio architectures that use digital modulation schemes require two analogue to digital converters (ADCs) in the receive path to convert respective quadrature (I and Q) signals. In radio frequency (RF) transceivers operating in receive mode, a large part of the overall current consumption is used by the ADCs to convert the quadrature ‘I’ and ‘Q’ signals from the analogue to the digital domain.
To address such problems associated with ADCs, architectures for implementing scalable resolution A/D converters and architectures for controlling dynamic ranges of an A/D converter have been investigated. For example, in U.S. Pat. No. 7,295,645 B1, a mechanism for dynamic selection of an ADC dynamic range using solely power is proposed.
Architectures and circuits and methods for improving the performance, and reducing the current consumption, of ADCs would therefore be useful.